Xilinx XC3S500E pin description
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| Signal | Description |
|---|---|
| IO_L.. | Can be used as single ended, or differential with N + P in conjuction |
| IP | Can only be used as inputs |
| GCLK | Global clock |
| A*, D*, LDC* | Addressable eeprom configuration |
| VS* | Variant Selection (for SPI eeprom?) |
See page 70/234 in datasheet.
