Difference between revisions of "RTL m68k"
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''Have you seen the [http://www.opencores.org/forums.cgi/cores/2000/03/00281 discussion at Open Cores]?'' | ''Have you seen the [http://www.opencores.org/forums.cgi/cores/2000/03/00281 discussion at Open Cores]?'' | ||
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| + | The most finished 68000 in VHDL I know of is from the Atari ST in VHDL: | ||
| + | [http://download.experiment-s.de/Suska/Configware/2K7A/rtl/vhdl/WF_68K00_IP/ Suska project : 68000 IP v2K7A] | ||
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[[Minimig Improvements]] | [[Minimig Improvements]] | ||
Revision as of 08:58, 29 July 2007
Is there a "soft core" m68k for FPGAs?
Haveing the cpu in vhdl/verilog would allow to eliminate the need for a special Minimig board. And being able to use plain developer boards from Xilinx or other manufactors.
Have you seen the discussion at Open Cores?
The most finished 68000 in VHDL I know of is from the Atari ST in VHDL: Suska project : 68000 IP v2K7A
