Difference between revisions of "Xilinx XC3S500E pin description"
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(IP) |
(VS) |
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| Line 10: | Line 10: | ||
|- | |- | ||
| A*, D*, LDC* || Addressable eeprom configuration | | A*, D*, LDC* || Addressable eeprom configuration | ||
| + | |- | ||
| + | | VS* || Variant Selection (for SPI eeprom?) | ||
|} | |} | ||
See page 70/234 in datasheet. | See page 70/234 in datasheet. | ||
Latest revision as of 06:57, 27 August 2007
| Signal | Description |
|---|---|
| IO_L.. | Can be used as single ended, or differential with N + P in conjuction |
| IP | Can only be used as inputs |
| GCLK | Global clock |
| A*, D*, LDC* | Addressable eeprom configuration |
| VS* | Variant Selection (for SPI eeprom?) |
See page 70/234 in datasheet.
