Difference between revisions of "Xilinx XC3S500E"
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Xilinx XC3S500E is logic optimized [[Field-programmable gate array|FPGA]].<br> | Xilinx XC3S500E is logic optimized [[Field-programmable gate array|FPGA]].<br> | ||
[[Xilinx XC3S500E pins]]<br> | [[Xilinx XC3S500E pins]]<br> | ||
| + | [[Xilinx XC3S500E pin description]]<br> | ||
[http://direct.xilinx.com/bvdocs/publications/ds312.pdf Xilinx Spartan-3E Datasheet]<br> | [http://direct.xilinx.com/bvdocs/publications/ds312.pdf Xilinx Spartan-3E Datasheet]<br> | ||
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| + | Default I/O standard for configuration: LVCMOS25<br> | ||
| + | By setting VCCO_2 to another value, one can use 1,8V or 3,3V operation aswell.<br> | ||
Latest revision as of 06:49, 27 August 2007
Xilinx XC3S500E is logic optimized FPGA.
Xilinx XC3S500E pins
Xilinx XC3S500E pin description
Xilinx Spartan-3E Datasheet
Default I/O standard for configuration: LVCMOS25
By setting VCCO_2 to another value, one can use 1,8V or 3,3V operation aswell.
