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Minimig NTSC fix code0 minimig1.v - Revision history
2024-03-28T23:21:27Z
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Freqmax: Ntsc fix code0 minimig1.v moved to Minimig NTSC fix code0 minimig1.v
2007-07-28T02:06:42Z
<p>Ntsc fix code0 minimig1.v moved to Minimig NTSC fix code0 minimig1.v</p>
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<td colspan="1" style="background-color: #fff; color: #222; text-align: center;">← Older revision</td>
<td colspan="1" style="background-color: #fff; color: #222; text-align: center;">Revision as of 02:06, 28 July 2007</td>
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Freqmax
http://www.opencircuits.com/index.php?title=Minimig_NTSC_fix_code0_minimig1.v&diff=5460&oldid=prev
Freqmax: code minimig1.v
2007-07-27T18:43:16Z
<p>code minimig1.v</p>
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<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">Revision as of 18:43, 27 July 2007</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>//Master clock generator for minimig</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>//Master clock generator for minimig</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>//This module generates all necessary clock from the 3.579545 NTSC clock</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>//This module generates all necessary clock from the 3.579545 NTSC clock</div></td></tr>
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Freqmax
http://www.opencircuits.com/index.php?title=Minimig_NTSC_fix_code0_minimig1.v&diff=5459&oldid=prev
Freqmax: code minimig1.v
2007-07-27T18:42:24Z
<p>code minimig1.v</p>
<p><b>New page</b></p><div>//Master clock generator for minimig<br />
//This module generates all necessary clock from the 3.579545 NTSC clock<br />
module clock_generator(mclk,c_28m,c_7m,cq_7m,e);<br />
input mclk; //3.579545 MHz master oscillator input<br />
output c_28m; //28.63636 MHz clock out<br />
output c_7m; //7.15909 MHz clock out<br />
output cq_7m; //7.15909 MHz qudrature clock out<br />
output e; //0.715909 MHz clock enable out<br />
<br />
reg ic_14m; //14.31818 MHz intermediate frequency <br />
reg ic_7m; <br />
reg icq_7m; <br />
<br />
reg [3:0]ediv; //used to generate e clock enable<br />
<br />
// Instantiate the DCM module<br />
// the DCM is configured to generator c_28m from mclk (multiply by 8)<br />
clock_dcm dcm1(<br />
.CLKIN_IN(mclk), <br />
.RST_IN(1'b0), <br />
.CLKFX_OUT(c_28m), <br />
.CLKIN_IBUFG_OUT(), <br />
.LOCKED_OUT()<br />
);<br />
<br />
//generator ic_14m<br />
always @(posedge c_28m)<br />
ic_14m<=~ic_14m;<br />
<br />
//generate ic_7m<br />
always @(posedge ic_14m)<br />
ic_7m<=~ic_7m;<br />
<br />
//generate icq_7m<br />
always @(negedge ic_14m)<br />
icq_7m<=ic_7m;<br />
<br />
//generate e<br />
always @(posedge c_7m)<br />
if(e)<br />
ediv<=9;<br />
else<br />
ediv<=ediv-1;<br />
assign e=(ediv==4'b0000)?1:0;<br />
<br />
<br />
//clock buffers<br />
BUFG buf1 ( .I(ic_7m), <br />
.O(c_7m) );<br />
BUFG buf2 ( .I(icq_7m), <br />
.O(cq_7m));<br />
<br />
endmodule</div>
Freqmax