Minimig FPGA

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Revision as of 11:39, 29 July 2007 by (talk)
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Switching from the Spartan 3 XC3S400 to a Spartan 3E XC3S500E would give you about 17 extra I/O pins while still keeping the 208 pin package. It would also give you a good bit of space for bug fixes and/or future enhancements. The current Minimig design uses up about 82% of the XC3S400, but only 65% of an XC3S500E.

Digikey sells them ;)

Use as a south bridge a CPLD like:
- Altera MAX 3000 EPM3128ATC100-10 (128 Macrocells, 80 IOs)
- Xilinx XL9500XL XC95144XL-10TQ100C (144 Macrocells, 81 IOs)

The slow IOs from paula and the 8520s can be moved to the CPLD.
On a real ECS/OCS Amiga, IOs from the 8520s are updated at 700 KHz, IOs from Paula are updated at 3.5 MHz.
On a real AGA Amiga, the 8520s are slightly faster : the IOs are updated at 1.4 MHz.
If we run a high speed bus at 28 Mhz between the FPGA and the CPLD, each wire can "transport" 8 IOs from paula or 20 IOs from a 8520.
The CPLD acts as a giant IO demultiplexer.
By the way the CPLD are 5V tolerant and non-volatile.