Difference between revisions of "Minimig FPGA"
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! Brand!! Chip!! LEs / LCs!! IOs!! Package
! Brand!! Chip!! LEs / LCs!! IOs!! PackagePrice
Revision as of 15:01, 29 July 2007
Switching from the Spartan 3 XC3S400 to a Spartan 3E XC3S500E would give you about 17 extra I/O pins while still keeping the 208 pin package. It would also give you a good bit of space for bug fixes and/or future enhancements. The current Minimig design uses up about 82% of the XC3S400, but only 65% of an XC3S500E.
Digikey sells them ;)
|Brand||Chip||LEs / LCs||IOs||Package||Price|
Altera chips are slighlty more expensive than Xilinx's.
It is worth considering the cyclone III if we want to integrate the 680x0 into the FPGA.
Use as a south bridge, a CPLD like:
|Altera||MAX 3000 EPM3128ATC100-10||128||80||$8.60||No|
freqmax: I think that considering Linux support + lower price + consistency with the main fpga. I think that the Xilinx option is better choice.
freqmax: Another consideration is that using an fpga instead of an cpld is that options for larger bus expansions like Zorro bus, Harddisc via ATA etc.. becomes viable. Due capability for faster fpga-fpga communications and more I/Os.
The slow IOs from Paula and the 8520s can be moved to the CPLD.
On a real ECS/OCS Amiga, IOs from the 8520s are updated at 700 KHz, IOs from Paula/Denise are updated at 3.5 MHz.
On a real AGA Amiga, the 8520s are slightly faster : the IOs are updated at 1.4 MHz.
If we run a high speed bus at 28 MHz between the FPGA and the CPLD, each wire can "transport" 8 IOs from paula or 20 IOs from a 8520.
The CPLD basically acts as a giant IO demultiplexer.
Moreover, the CPLDs are 5V tolerant and non-volatile.
There is an application note from Altera describing how to use a MAX as an IO expander :
AN 265: Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander