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Use as a south bridge, a CPLD like:<br>
 
Use as a south bridge, a CPLD like:<br>
 
{| class="wikitable"
 
{| class="wikitable"
! Brand!! Chip!! Macrocells!! IOs!! Price!! Free Place%Route Linux support
+
! Brand!! Chip!! Macrocells!! IOs!! Price!! Linux support
 
|-  
 
|-  
 
| Altera|| MAX 3000 EPM3128ATC100-10|| 128 || 80 || $8.60||No
 
| Altera|| MAX 3000 EPM3128ATC100-10|| 128 || 80 || $8.60||No
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<br>
 
<br>
 
The slow IOs from Paula and the 8520s can be moved to the CPLD.<br>
 
The slow IOs from Paula and the 8520s can be moved to the CPLD.<br>
On a real ECS/OCS Amiga, IOs from the 8520s are updated at 700 kHz, IOs from Paula/Denise are updated at 3.5 MHz.<br>
+
On a real ECS/OCS Amiga, IOs from the 8520s are updated at 700 KHz, IOs from Paula/Denise are updated at 3.5 MHz.<br>
 
On a real AGA Amiga, the 8520s are slightly faster : the IOs are updated at 1.4 MHz.<br>
 
On a real AGA Amiga, the 8520s are slightly faster : the IOs are updated at 1.4 MHz.<br>
 
If we run a high speed bus at 28 MHz between the FPGA and the CPLD, each wire can "transport" 8 IOs from paula or 20 IOs from a 8520.<br>
 
If we run a high speed bus at 28 MHz between the FPGA and the CPLD, each wire can "transport" 8 IOs from paula or 20 IOs from a 8520.<br>
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There is an application note from Altera describing how to use a MAX as an IO expander :<br>
 
There is an application note from Altera describing how to use a MAX as an IO expander :<br>
 
[http://www.altera.com/literature/an/an265.pdf AN 265: Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander]
 
[http://www.altera.com/literature/an/an265.pdf AN 265: Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander]
 
[[Xilinx XC3S400 and XC3S500E comparison]]<br>
 
[[Xilinx XC3S500E]]<br>
 
[[Xilinx XC3S500E pins]]<br>
 
 
schmartboard.com adapter:
 
:The largest Xilinx Spartan-3 FPGA that has less than 400 pins (20x20 matrix) is the FG320 package: http://direct.xilinx.com/bvdocs/publications/ds099.pdf
 
:(FG320 XC3S1500 is also the largest FPGA with Webpack support)
 
 
:The FG320 package is an 18x18 matrix with 1mm pitch: http://www.xilinx.com/bvdocs/packages/fg320.pdf
 
 
:Schmartboard 202-0026-01 is BGA 400 Pins, 1.0 mm Pitch: http://www.schmartboard.com/index.asp?page=products_bga&id=110
 
 
:Diagram of 202-0026-01: http://www.schmartboard.com/schmartboard_pd_202-0026-01.pdf
 
 
:It would be benefitial if someone can clarify this matter.
 
 
Actel FPGA option:
 
:[http://www.actel.com/products/pa3/ Actel FPGA] [http://www.amiga.org/modules/newbb/viewtopic.php?topic_id=39358&forum=8&viewmode=flat&order=ASC&start=200 Unit01 070731]
 
 
Xilinx Webpack support maximum: XC3S1500 XC3S1600E
 

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