Minimig Board v1.0 issues
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Schematics: Minimig Board v1.0 schematic
- Include a +5V regulator on board OR use an ATX-style powerplug if you go Mini-ITX. The +5V regulator should be capable of providing about 1A to safely power all peripherals one might attach.
- Hardwire the patch needed to get the current board to run. Alternatively, you can also swap pin 81 and pin 79 on the FPGA. This way you still have four user-IO's left. You do need to change the .UCF file though and recompile the core.
- PATCH needed to get rev 1 board working:
- Disconnect net SPI_DOUT from pin 81 of FPGA.
- Connect net SPI_DOUT to pin 19 of FPGA (net USER3).
- Reason:
- Pin 81 is an output during FPGA config that blocks SPI to MMC during startup.
- The MMC card interface has a resistor based clock gate circuit around R50,R51. This should be replaced with a proper (single) gate "OR" chip. The margins on this signal are pretty tight on the current board. Also, R49 should be 0 ohm ideally to avoid problems when upgrading the PIC to a newer PIC18LF2620 or something similair. Margins are tight on that signal too atm.
- You could consider using a single 20MHz oscillator and figure out how to program the DCM to generator the proper clocks, this would spare a crystal.
- Why is the cpu pin 19 not connected to anything ?
- The 68SEC000 is run in 16bit (selected by pin 8) mode, which means that only even addresses are used, hence the lsb address select is not needed.
- The addressing of byte wide memory addresses is done using the LDS/UDS strobes.
- Peak & average powerconsumption of the minimig v1 ..?
- From what I have seen the power consumption is pretty constant. All boards I've built so far consume about 100mA (excluding keyboard/mouse).
- Any power or grounding issues?
- I did use a "local-plane" setup. I have set most IO's to slow slewrates and drive currents.
- Why does the sram use /UB and /LB when data is 16-bit anyway?
- jkonstan 070801:
- The UB & LB strobes on the SRAM are due to data bus addressing needed for the 68K cpu. 68K CPU has UDS* strobe for upper byte lane D15-D8 access, and 68K CPU has LDS* strobe for lower byte lane D7-D0 access. When 68K does a read, D15-D0 can be accessed as a word with 68K reading what it requires off of its Databus; however, a write access on a 68K CPU requires the byte lane be qualified. When UDS* active on a write cycle, UB* on SRAM must be active. When LDS* active on a write cycle, LB* on SRAM must be active.
D15........D8 D7........D0 Byte 0= Even Byte 1= Odd => (Word 0) /UDS /LDS etc..
- Ie 68k writes are byte wide.
- The SD-MMC slot has a 12-pin wide connection to pcb.
- CD/D3, CMD, GND, VDD, CLOCK, GND, D0, D1, D2, SW#1, SW#2, SW#3
- SW#1="gnd", SW#2=open=>write protect, SW#3=open=>no card present
- Why is address/data pins to ram/cpu spread around despite dedicated board?
- Became such way to ease the PCB layout.
- Using 1Mx16 bit ram will free RAM_SEL1
- FPGA pin 54,55,56 M1,M0,M2 configuration mode pins use VccAUX => +2.5V
- SPI_DOUT from SD-Card via 1k resistor and FPGA(pin81) conflicts ..?
- A gate would be better. During normal operation, the SPI out of the MMC card is tristated by disabling the MMC, the same goes at the FPGA side (it's a tristate port). This way, they can share the SPI bus.
- Keyboard and mouse can share connection?
- Won't save data lines.
- Over/under voltage protection for keyboard or mouse port?
- It is a minimal design. The Spartan has built-in ESD protection that this design relies on. :However, monitors and TV's are notorious for blowing up video ports so extra protection has been added there!
- BAV99 diodes in the schematic is 3-pin not 2-pin as can be thought.
- Headphones may cause back-emf? (maybe supposed to be used as line-out only?)
- 15/31kHz selector is missing reference designation.
- Component size is missing.
- +1.25V and +2.5V can be hooked from +3.3V to save power ?
- No gain
- Why FPGA I/O pins aren't in numerical order?
- Was simple when starting out.
- Value of C37 100uF/6.3V?
- Yes
- Why is R42 present, it's just sitting between +1,25V and GND?
- Provides a minimum load for the LM1117.
- MCU(pic18) & FPGA TxD via AND-gate to rid of one jumper:
- Yes, no problem. However, all debug output of the PIC has to be disabled as not to interfer with the FPGA serial output.
- Crystals X1 and X2 is operating in parallel or serial mode ?
- Video D/A have inconsistent resistor values. Use another prefered number series?
- Uses 4000, 2000, 1000, 560 ohm per color presently.
- Video, in 15kHz mode:
- /VSYNC = high (scart RGB enable)
- /HSYNC = composite sync
- Connection, RS232:
- Connection, Audio:
- internal x86-pc cdrom -> soundcard analogue audio pinout
- Voltage level: (3.3V/(560ohm + 560ohm + 32ohm))*32 ohm*1000 = 91,7mV
- Some SD/MMC cards aren't standards compliant! see 1541-III FAQ
Xilinx ISE Webpack device support
- Free version supports Spartan3 XC3S50 - XC3S1500
