Minimig 68K CPU BERR* Support

We can connect one of the spare FPGA pins (such as USER I/O 3) to BERR* on the MC68SEC000 so that we can generate a Bus error exception to 68K CPU when bad code addresses non-existant memory. A Verilog code module to implement this function would be simple (equivalent to a single 74LCX164 or about 5 to 10 lines of Verilog in the Spartan3). I think that the Guru meditation Errors from Amiga OS support reporting BERR* Vector.

M68k bus cycle seems to be like this:

CPU activates AS (Address strobe)

A valid device will respond by activating DTACK (Data transfer acknowledge)

If there's no device a timeout circuit will activate BERR (Bus error). Such that the cpu knows there's nothing there.

It seems BERR is not stricly needed. I presume current implementation happily answers any address with DTACK :-) Is there any software that (ab)use BERR?