Difference between revisions of "RTL m68k"
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The most finished 68000 in VHDL I know of is from the Atari ST in VHDL: | The most finished 68000 in VHDL I know of is from the Atari ST in VHDL: | ||
[http://download.experiment-s.de/Suska/Configware/2K7A/rtl/vhdl/WF_68K00_IP/ Suska project : 68000 IP v2K7A] | [http://download.experiment-s.de/Suska/Configware/2K7A/rtl/vhdl/WF_68K00_IP/ Suska project : 68000 IP v2K7A] | ||
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| + | : Would it make any sense to replace the "FPGA chip + CPU chip" on the current Minimig, with a single-chip "FPGA + CPU chip" device? --[[User:DavidCary|DavidCary]] 21:28, 28 July 2007 (PDT) | ||
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| + | [http://www.amiga.org/modules/newbb/viewtopic.php?topic_id=39358&forum=8&viewmode=flat&order=ASC&start=8#forumpost465986 TobiFlex 070826 13:39]<br> | ||
| + | This CPU Core is not finish. The Debuging must go on. Currently hangs up this CPU Core with Kickstartrom 2.04 at #$F81914. | ||
| + | |||
| + | [http://www.amiga.org/modules/newbb/viewtopic.php?topic_id=39358&forum=8&viewmode=flat&order=ASC&start=8#forumpost465988 TobiFlex 070826 14:06]<br> | ||
| + | I have adapted the minimig Core to the DE2 Board from Terasic with a ALTERA Cyclone 2C35. With an external CPU MC68HC000 runs the Minimig perfekt. I have change the RAM Timing from SRAM to SDRAM - so i can use the on Board SDRAM Chip. | ||
| + | And now i use the Board to Debug Wolfgangs 68K Core. | ||
| + | |||
| + | [http://www.amiga.org/modules/newbb/viewtopic.php?topic_id=39358&forum=8&viewmode=flat&order=ASC&start=8#forumpost466035 mongo 070826 20:25]<br> | ||
| + | Wolfgang's 68K core will run up to about 17 MHz in a Spartan 3. | ||
| − | [ | + | [http://www.amiga.org/modules/newbb/viewtopic.php?topic_id=39358&forum=8&viewmode=flat&order=ASC&start=8#forumpost466058 jkonstan 070826 21:23]<br> |
| + | external CBT16245 level shifters | ||
Revision as of 12:46, 26 August 2007
Is there a "soft core" m68k for FPGAs?
Haveing the cpu in vhdl/verilog would allow to eliminate the need for a special Minimig board. And being able to use plain developer boards from Xilinx or other manufactors.
Have you seen the discussion at Open Cores?
The most finished 68000 in VHDL I know of is from the Atari ST in VHDL: Suska project : 68000 IP v2K7A
- Would it make any sense to replace the "FPGA chip + CPU chip" on the current Minimig, with a single-chip "FPGA + CPU chip" device? --DavidCary 21:28, 28 July 2007 (PDT)
TobiFlex 070826 13:39
This CPU Core is not finish. The Debuging must go on. Currently hangs up this CPU Core with Kickstartrom 2.04 at #$F81914.
TobiFlex 070826 14:06
I have adapted the minimig Core to the DE2 Board from Terasic with a ALTERA Cyclone 2C35. With an external CPU MC68HC000 runs the Minimig perfekt. I have change the RAM Timing from SRAM to SDRAM - so i can use the on Board SDRAM Chip.
And now i use the Board to Debug Wolfgangs 68K Core.
mongo 070826 20:25
Wolfgang's 68K core will run up to about 17 MHz in a Spartan 3.
jkonstan 070826 21:23
external CBT16245 level shifters
