Difference between revisions of "Minimig Board v1.0 schematic"

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(layout fixed)
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Board schematic for Minimig board v1.0
 
Board schematic for Minimig board v1.0
−
[[Image:Minimig_v10_board_audio.png|thumb|right|250px|Audio output]]
+
[[Image:Minimig_v10_board_audio.png|thumb|right|250px|Audio output via 3,5mm jack]]
 
Voltage level: (3.3V/(560ohm + 560ohm + 32ohm))*32 ohm*1000 = 91,7mV<br>
 
Voltage level: (3.3V/(560ohm + 560ohm + 32ohm))*32 ohm*1000 = 91,7mV<br>
−
[[Back EMF]] issues?
+
[[Back EMF]] issues?<br>
 +
[http://en.wikipedia.org/wiki/Headphone Head phones]<br>
  
 
[[Image:Minimig_v10_board_dac.png|thumb|right|250px|4 bit resistor ladder D/A]]
 
[[Image:Minimig_v10_board_dac.png|thumb|right|250px|4 bit resistor ladder D/A]]
 
Notice the resistor of 560 ohm. May cause inlinear output.<br>
 
Notice the resistor of 560 ohm. May cause inlinear output.<br>
  
−
[[Image:Minimig_v10_board_fpga.png|thumb|right|250px|FPGA Xilinx XC3S400-4PQ208C]]
+
[[Image:Minimig_v10_board_fpga.png|thumb|right|250px|[[FPGA]] Xilinx XC3S400-4PQ208C]]
 +
 
 +
[[Image:Minimig_v10_board_fpga_core_pwr.png|thumb|right|250px|FPGA core power +1,25V +2,5V using [http://www.national.com/pf/LM/LM1117.html LM1117MP-ADJ] ]]
  
−
[[Image:Minimig_v10_board_fpga_core_pwr.png|thumb|right|250px|FPGA core power +1,25V +2,5V using  [http://www.national.com/pf/LM/LM1117.html LM1117MP-ADJ]]]
 
 
[[Image:Minimig_v10_board_fpga_decoupling.png|thumb|right|250px|FPGA [[decoupling]]]]
 
[[Image:Minimig_v10_board_fpga_decoupling.png|thumb|right|250px|FPGA [[decoupling]]]]
 
[[Image:Minimig_v10_board_joy0.png|thumb|right|250px|Joystick 0]]
 
[[Image:Minimig_v10_board_joy0.png|thumb|right|250px|Joystick 0]]
 
[[Image:Minimig_v10_board_joy1.png|thumb|right|250px|Joystick 1]]
 
[[Image:Minimig_v10_board_joy1.png|thumb|right|250px|Joystick 1]]
−
[[Image:Minimig_v10_board_jtag.png|thumb|right||[[Jtag]]]]
+
[[Image:Minimig_v10_board_jtag.png|thumb|right|| [[Jtag]] ]]
−
[[Image:Minimig_v10_board_jumpers.png|thumb|right|250px|Jumper]]
+
[[Image:Minimig_v10_board_jumpers.png|thumb|right|250px|Program & Menu button, 31/15kHz selection, Power & Disc led]]
 
[[Image:Minimig_v10_board_kbd_mouse.png|thumb|right|250px|[[Keyboard]] & [[Mouse]] connections]]
 
[[Image:Minimig_v10_board_kbd_mouse.png|thumb|right|250px|[[Keyboard]] & [[Mouse]] connections]]
 
[[Image:Minimig_v10_board_m68k.png|thumb|right|250px|MC68000]]
 
[[Image:Minimig_v10_board_m68k.png|thumb|right|250px|MC68000]]
−
[[Image:Minimig_v10_board_m68k_decoupling.png|thumb|right|250px|MC68000 [[Decoupling]]]]
+
[[Image:Minimig_v10_board_m68k_decoupling.png|thumb|right||MC68000 [[Decoupling]] ]]
−
[[Image:Minimig_v10_board_mclk_generator.png|thumb|right|250px|Generation of 4.433619 MHz [[PAL]] Video MCLK using [http://www.it.lth.se/datablad/Logik/74HC/74HC4060.pdf 74HC4060] (Ntsc=3.579545MHz)]]
+
[[Image:Minimig_v10_board_mclk_generator.png|thumb|right|250px|Generation of 4.433619 MHz [[PAL]] video MCLK using [http://www.it.lth.se/datablad/Logik/74HC/74HC4060.pdf 74HC4060] (NTSC=3.579545MHz)]]
−
PATCH needed to get rev 1 board working:<br>
+
PATCH needed to get rev 1 board working:
 
:Disconnect net SPI_DOUT from pin 81 of FPGA.
 
:Disconnect net SPI_DOUT from pin 81 of FPGA.
 
:Connect net SPI_DOUT to pin 19 of FPGA (net USER3).
 
:Connect net SPI_DOUT to pin 19 of FPGA (net USER3).
 
:
 
:
−
;REASON:
+
:REASON:
 
:Pin 81 is an output during FPGA config that blocks SPI to MMC during startup.
 
:Pin 81 is an output during FPGA config that blocks SPI to MMC during startup.
  
−
[[Image:Minimig_v10_board_pic18.png|thumb|right|250px|[[MCU]] [http://ww1.microchip.com/downloads/en/devicedoc/39564b.pdf PIC18LF252I/SP]]]
+
[[Image:Minimig_v10_board_pic18.png|thumb|right|250px|[[MCU]] [http://ww1.microchip.com/downloads/en/devicedoc/39564b.pdf PIC18LF252I/SP] ]]
 +
 
 
[[Image:Minimig_v10_board_ram512x16.png|thumb|right|250px|[[Asynchronous static ram]] 512 x 16 bit (2 chips)]]
 
[[Image:Minimig_v10_board_ram512x16.png|thumb|right|250px|[[Asynchronous static ram]] 512 x 16 bit (2 chips)]]
−
[[Image:Minimig_v10_board_rs232.png|thumb|right|250px|Serial [[RS232]] using [http://datasheets.maxim-ic.com/en/ds/MAX220-MAX249.pdf MAX232]]]
+
 
 +
[[Image:Minimig_v10_board_rs232.png|thumb|right|250px|Serial [[RS232]] using [http://datasheets.maxim-ic.com/en/ds/MAX220-MAX249.pdf MAX232] ]]
 +
 
 
[[Image:Minimig_v10_board_sd_card.png|thumb|right|250px|[[SD Card]] slot]]
 
[[Image:Minimig_v10_board_sd_card.png|thumb|right|250px|[[SD Card]] slot]]
−
[[Image:Minimig_v10_board_spare_io.png|thumb|right||Spare I/O]]
+
[[Image:Minimig_v10_board_spare_io.png|thumb|right||Spare I/O directly connected to FPGA]]

Revision as of 05:49, 2 August 2007

Board schematic for Minimig board v1.0

Audio output via 3,5mm jack

Voltage level: (3.3V/(560ohm + 560ohm + 32ohm))*32 ohm*1000 = 91,7mV
Back EMF issues?
Head phones

4 bit resistor ladder D/A

Notice the resistor of 560 ohm. May cause inlinear output.

FPGA Xilinx XC3S400-4PQ208C
FPGA core power +1,25V +2,5V using LM1117MP-ADJ
FPGA decoupling
Joystick 0
Joystick 1
Jtag
Program & Menu button, 31/15kHz selection, Power & Disc led
Keyboard & Mouse connections
MC68000
MC68000 Decoupling
Generation of 4.433619 MHz PAL video MCLK using 74HC4060 (NTSC=3.579545MHz)

PATCH needed to get rev 1 board working:

Disconnect net SPI_DOUT from pin 81 of FPGA.
Connect net SPI_DOUT to pin 19 of FPGA (net USER3).
REASON:
Pin 81 is an output during FPGA config that blocks SPI to MMC during startup.
MCU PIC18LF252I/SP
Asynchronous static ram 512 x 16 bit (2 chips)
Serial RS232 using MAX232
SD Card slot
Spare I/O directly connected to FPGA
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