Difference between revisions of "Field-programmable gate array"

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FPGA is a logic matrix configurable chip.
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A '''Field-Programmable Gate Array''' (FPGA) is a general purpose logic matrix configurable integrated circuit.  It consists of a collection of logic gates that can be connected together in an almost unlimited number of combinations to produce custom operations that would normally only be possible with full-custom integrated circuits.  Since FPGAs are produced in high volume, they can bring economies of scale to one-off and low volume projects.
  
 
Several open hardware projects use FPGAs, such as
 
Several open hardware projects use FPGAs, such as
 
* [[Minimig FPGA]]
 
* [[Minimig FPGA]]
 
* ...
 
* ...
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* [[Projects#Balloon_Xscale_ARM.2BFPGA_dev_board | Balloon Xscale + FPGA board]]
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* [[Motherboards that run Linux#Balloon_Xscale_ARM.2BFPGA_dev_board | Balloon Xscale + FPGA board]]
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* [[RTL m68k]]
 
* [[WikiNode | The Open Graphics Project]] (OGP) is developing graphics cards with fully published specs and open source drivers. Since the first version will be a FPGA, is also collecting information on FPGA programming and interfacing.
 
* [[WikiNode | The Open Graphics Project]] (OGP) is developing graphics cards with fully published specs and open source drivers. Since the first version will be a FPGA, is also collecting information on FPGA programming and interfacing.
 
* ...
 
* ...
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[[Xilinx]] ...
 
[[Xilinx]] ...
 
[[Altera]] ...
 
[[Altera]] ...
 +
[[Lattice]] ...
  
 +
== Verilog ==
 +
Verilog is a hardware description language (HDL) used to model electronic systems. The language (sometimes called Verilog HDL) supports the design, verification, and implementation of analog, digital, and mixed-signal circuits at various levels of abstraction.
  
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== further reading ==
+
== VHDL ==
 +
VHDL (VHSIC hardware description language) is commonly used as a design-entry language for designing digital circuits as field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).
  
 +
== History ==
 +
 +
... standard logic devices ...
 +
 +
The 1978 programmable array logic ([[PAL]]) was a revolutionary device.
 +
Previous CPUs were built from a rack of PCBs full of of TTL ICs ([[standard logic CPU]]);
 +
PALs allowed CPUs that were just as complex to be built from far fewer ICs on less than a dozen PCBs.
 +
The book "Soul of a New Machine" described the development
 +
of the "Eagle", one of the first CPUs to use PALs rather than fixed-function TTL ICs ([[TTL CPU]]).<ref>
 +
[https://www.embeddedrelated.com/showthread/fpga-cpu/1193-1.php "PAL/GAL CPUs?"].
 +
</ref>
 +
PAL chips were first introduced in 1978 by MMI (now part of Lattice Semiconductor) and soon second sourced by National Semiconductor, Texas Instruments and AMD.
 +
 +
GAL devices are direct replacements for most PAL, EPLD, and PEEL devices.<ref>
 +
Lattice Semiconductor.
 +
[https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/CopyingPALEPLDandPEELPatternsintoGALDevices.ashx?la=en "Copying PAL, EPLD and PEEL Patterns into GAL Devices"].
 +
2002.
 +
</ref>
 +
The advantage of GAL and PEEL is that they can be quickly erased and re-programmed, unlike PALs which have one-time-programmable fuses or EPLDs which can only slowly be erased with ultraviolet light through a glass window.
 +
 +
The ispGAL devices are a further improvement: they have JTAG port that supports in-system programmability (ISP), unlike earlier devices that need to be socketed to allow pulling them out of the system, then plugging in a freshly-programmed device. (That JTAG port also supports internal and board-level testing).<ref>
 +
[https://www.latticesemi.com/support/answerdatabase/2/4/245 "What is the difference between an ispGAL and a GAL device?"]
 +
</ref>
 +
 +
SPLDs ...
 +
 +
CPLDs ... further improve density ...
 +
...
 +
 +
FPGAs ... are even more dense -- entire CPUs can be implemented on a single FPGA IC.
 +
Some FPGAs have enough capacity to implement multiple CPUs ...
 +
but they have some drawbacks:
 +
* most FPGAs reload their configuration on power-up, unlike CPLDs and SPLDs which are instant-on.
 +
* CPLDs and SPLDs have more predictable timing delays
 +
* SPLDs often have several second sources
 +
* building something with some specific FPGA seems to force the designer to use one specific proprietary software tool on one of a narrow range of specific proprietary OSes.<ref>
 +
Dieter Mueller 2004.
 +
[http://www.6502.org/users/dieter/mt15/mt15.htm "MT15"].
 +
quote: "If there would be a standard with FPGAs/CPLDs
 +
... allowing me to select
 +
between parts from different manufacturers with the
 +
same Pin_out while still working with the same
 +
(non_proprietary/open_source) software tools,
 +
this project would not exist."
 +
</ref>
 +
* ...
 +
 +
 +
 +
== Further reading ==
 
* [http://en.wikipedia.org/wiki/Field-programmable_gate_array Wikipedia: field-programmable gate array]
 
* [http://en.wikipedia.org/wiki/Field-programmable_gate_array Wikipedia: field-programmable gate array]
−
 
+
* [http://wiki.opengraphics.org/ The Open Graphics Project wiki]: The Open Graphics Project (OGP) is developing graphics cards with Free-licensed specifications and Free Software drivers. The FPGA development board OGD1, Revision B, uses a Xilinx® Spartan™-III XC3S4000 FPGA (primary FPGA) and a Lattice® LFXP10 non-volatile FPGA (PCI interface)
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----
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* [http://wacco.mveas.com/ "Project VGA"]: Home of the Low Budget, Open Source, VGA Compatible video card. Uses Xilinx Spartan 3 s400 FPGA.

Latest revision as of 12:29, 23 November 2022

A Field-Programmable Gate Array (FPGA) is a general purpose logic matrix configurable integrated circuit. It consists of a collection of logic gates that can be connected together in an almost unlimited number of combinations to produce custom operations that would normally only be possible with full-custom integrated circuits. Since FPGAs are produced in high volume, they can bring economies of scale to one-off and low volume projects.

Several open hardware projects use FPGAs, such as

Verilog ... Xilinx ... Altera ... Lattice ...

Verilog[edit]

Verilog is a hardware description language (HDL) used to model electronic systems. The language (sometimes called Verilog HDL) supports the design, verification, and implementation of analog, digital, and mixed-signal circuits at various levels of abstraction.

VHDL[edit]

VHDL (VHSIC hardware description language) is commonly used as a design-entry language for designing digital circuits as field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).

History[edit]

... standard logic devices ...

The 1978 programmable array logic (PAL) was a revolutionary device. Previous CPUs were built from a rack of PCBs full of of TTL ICs (standard logic CPU); PALs allowed CPUs that were just as complex to be built from far fewer ICs on less than a dozen PCBs. The book "Soul of a New Machine" described the development of the "Eagle", one of the first CPUs to use PALs rather than fixed-function TTL ICs (TTL CPU).<ref> "PAL/GAL CPUs?". </ref> PAL chips were first introduced in 1978 by MMI (now part of Lattice Semiconductor) and soon second sourced by National Semiconductor, Texas Instruments and AMD.

GAL devices are direct replacements for most PAL, EPLD, and PEEL devices.<ref> Lattice Semiconductor. "Copying PAL, EPLD and PEEL Patterns into GAL Devices". 2002. </ref> The advantage of GAL and PEEL is that they can be quickly erased and re-programmed, unlike PALs which have one-time-programmable fuses or EPLDs which can only slowly be erased with ultraviolet light through a glass window.

The ispGAL devices are a further improvement: they have JTAG port that supports in-system programmability (ISP), unlike earlier devices that need to be socketed to allow pulling them out of the system, then plugging in a freshly-programmed device. (That JTAG port also supports internal and board-level testing).<ref> "What is the difference between an ispGAL and a GAL device?" </ref>

SPLDs ...

CPLDs ... further improve density ... ...

FPGAs ... are even more dense -- entire CPUs can be implemented on a single FPGA IC. Some FPGAs have enough capacity to implement multiple CPUs ... but they have some drawbacks:

  • most FPGAs reload their configuration on power-up, unlike CPLDs and SPLDs which are instant-on.
  • CPLDs and SPLDs have more predictable timing delays
  • SPLDs often have several second sources
  • building something with some specific FPGA seems to force the designer to use one specific proprietary software tool on one of a narrow range of specific proprietary OSes.<ref>

Dieter Mueller 2004. "MT15". quote: "If there would be a standard with FPGAs/CPLDs ... allowing me to select between parts from different manufacturers with the same Pin_out while still working with the same (non_proprietary/open_source) software tools, this project would not exist." </ref>

  • ...


Further reading[edit]

  • Wikipedia: field-programmable gate array
  • The Open Graphics Project wiki: The Open Graphics Project (OGP) is developing graphics cards with Free-licensed specifications and Free Software drivers. The FPGA development board OGD1, Revision B, uses a Xilinx® Spartan™-III XC3S4000 FPGA (primary FPGA) and a Lattice® LFXP10 non-volatile FPGA (PCI interface)
  • "Project VGA": Home of the Low Budget, Open Source, VGA Compatible video card. Uses Xilinx Spartan 3 s400 FPGA.
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