Difference between revisions of "Minimig SDram"
Jump to navigation
Jump to search
(sdram why) |
(CPU UB-LB signals knowhow) |
||
| (One intermediate revision by one other user not shown) | |||
| Line 1: | Line 1: | ||
Advantages: | Advantages: | ||
| − | + | ;Cheaper and more memory. | |
| + | :Run faster : a 114 Mhz Chip-RAM is possible. | ||
| + | :Consume less FPGA I/Os (especialy the DDR-SDRAM) | ||
Disadvantages: | Disadvantages: | ||
| − | + | :Uses pipeline (complicated!) | |
| − | + | :PCB traces must have the same length and a 50 ohm impedance. | |
| + | |||
| + | [http://www.amiga.org/modules/newbb/viewtopic.php?topic_id=39358&forum=8&viewmode=flat&order=ASC&start=240 jkonstan 070801]:<br> | ||
| + | :The UB & LB strobes on the SRAM are due to data bus addressing needed for the 68K cpu. 68K CPU has UDS* strobe for upper byte lane D15-D8 access, and 68K CPU has LDS* strobe for lower byte lane D7-D0 access. When 68K does a read, D15-D0 can be accessed as a word with 68K reading what it requires off of its Databus; however, a write access on a 68K CPU requires the byte lane be qualified. When UDS* active on a write cycle, UB* on SRAM must be active. When LDS* active on a write cycle, LB* on SRAM must be active. | ||
| + | : | ||
| + | :D15 ........D8,,,,,,,,,D7........D0 | ||
| + | :Byte 0= Even,,,,,,,,Byte 1= Odd => (Word 0) | ||
| + | :/UDS ,,,,,,,,,,,,,,,,,,,/LDS | ||
Latest revision as of 13:23, 1 August 2007
Advantages:
- Cheaper and more memory.
- Run faster : a 114 Mhz Chip-RAM is possible.
- Consume less FPGA I/Os (especialy the DDR-SDRAM)
Disadvantages:
- Uses pipeline (complicated!)
- PCB traces must have the same length and a 50 ohm impedance.
- The UB & LB strobes on the SRAM are due to data bus addressing needed for the 68K cpu. 68K CPU has UDS* strobe for upper byte lane D15-D8 access, and 68K CPU has LDS* strobe for lower byte lane D7-D0 access. When 68K does a read, D15-D0 can be accessed as a word with 68K reading what it requires off of its Databus; however, a write access on a 68K CPU requires the byte lane be qualified. When UDS* active on a write cycle, UB* on SRAM must be active. When LDS* active on a write cycle, LB* on SRAM must be active.
- D15 ........D8,,,,,,,,,D7........D0
- Byte 0= Even,,,,,,,,Byte 1= Odd => (Word 0)
- /UDS ,,,,,,,,,,,,,,,,,,,/LDS
