Difference between revisions of "Minimig"
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[[Image:Minimig 2890.jpg|thumb|right|250px|Minimig 120x120[[Millimetre|mm]] PCB board]] | [[Image:Minimig 2890.jpg|thumb|right|250px|Minimig 120x120[[Millimetre|mm]] PCB board]] | ||
[[#See also|QUICKLINK]]<br> | [[#See also|QUICKLINK]]<br> | ||
| Line 30: | Line 28: | ||
* Creating something for the community. | * Creating something for the community. | ||
* Proof of Concept. | * Proof of Concept. | ||
| − | * Can create new games to take advantages of the new features in Minimig (faster memory, more memory sprites, colours, etc), while maintaining full compatibility with the classic Amiga. | + | * Can create new games to take advantages of the new features in Minimig (faster memory, more memory, sprites, colours, etc), while maintaining full compatibility with the classic Amiga. |
| + | * Make the Amiga custom chip technology concept available under GPL. | ||
== Hardware == | == Hardware == | ||
| Line 36: | Line 35: | ||
* [[Xilinx#Spartan series|Xilinx Spartan-3]] 400k gate (XC3S400-4PQ208C) FPGA using 60% capacity. | * [[Xilinx#Spartan series|Xilinx Spartan-3]] 400k gate (XC3S400-4PQ208C) FPGA using 60% capacity. | ||
| − | * [[Freescale Semiconductor|Freescale]] MC68SEC000 (MC68SEC000FU20; MC68SEC000AA20 proposed as replacement part by Freescale), 3,3[[Volt|V]], at 7.09379 [[Hertz|MHz]]. (However there's no 'E' clock, MOVE sr,<EA> is privileged and there is no real replacement instruction. This does not seem to affect any programs as of yet however.) | + | * [[Freescale Semiconductor|Freescale]] MC68SEC000 (MC68SEC000FU20; MC68SEC000AA20 proposed as replacement part by Freescale), 3,3[[Volt|V]], running programable at 7.09379 and 14.18758 [[Hertz|MHz]]. (However there's no 'E' clock, MOVE sr,<EA> is privileged and there is no real replacement instruction. This does not seem to affect any programs as of yet however.) |
* Amiga ChipRAM bus and FastRAM merged into a single synchronous bus running at 7.09379 MHz. | * Amiga ChipRAM bus and FastRAM merged into a single synchronous bus running at 7.09379 MHz. | ||
* 2 [[Mebibyte|MB]] 70 [[1 E-9 s|ns]] [[Static random access memory|SRAM]] organised as 2 524288*16 banks. | * 2 [[Mebibyte|MB]] 70 [[1 E-9 s|ns]] [[Static random access memory|SRAM]] organised as 2 524288*16 banks. | ||
* [[Microcontroller|MCU]] [[PIC microcontroller#PIC18 High End Core Devices|PIC 18LF252-I/SP]] <ref>{{cite web|title=PIC18F252|url=http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1335&dDocName=en010276}} 070715 microchip.com</ref> (an alternative would be [[Atmel AVR]]) implements a [[File Allocation Table|FAT16]] disclayout and handles loading of fpga configuration and kickstart. Simulates a floppy to the Amiga by encoding on the fly from [[Amiga Disk File|.ADF]] files. <!-- This is NOT the TNT23 project. --> | * [[Microcontroller|MCU]] [[PIC microcontroller#PIC18 High End Core Devices|PIC 18LF252-I/SP]] <ref>{{cite web|title=PIC18F252|url=http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1335&dDocName=en010276}} 070715 microchip.com</ref> (an alternative would be [[Atmel AVR]]) implements a [[File Allocation Table|FAT16]] disclayout and handles loading of fpga configuration and kickstart. Simulates a floppy to the Amiga by encoding on the fly from [[Amiga Disk File|.ADF]] files. <!-- This is NOT the TNT23 project. --> | ||
* [[Multi Media Card|MMC]] [[Flash memory|Flash memory card]] to load fpga configuration, kickstart and software for the simulated computer. | * [[Multi Media Card|MMC]] [[Flash memory|Flash memory card]] to load fpga configuration, kickstart and software for the simulated computer. | ||
| − | * | + | * 3 [[Light-emitting diode|LED]]s to display the system status - Main power (blue) - Amiga Power (red) - Drive activity (green). |
| − | * Video [[Digital-to-analog converter|D/A]] consists of 4 [[resistor|resistors]] for each color red, green, blue (4 bits/color) and output via [[Video Graphics Array|VGA]] connector. | + | * Video [[Digital-to-analog converter|D/A]] consists of 4 [[resistor|resistors]] for each color red, green, blue (4 bits/color) and output via [[Video Graphics Array|VGA]] connector. [http://minimig.googlecode.com/files/minimig11_schematics.pdf Minimig schematics v1] Page3 |
* Audio from an 8 bit [[dither|dithering]] [[Delta-sigma modulation|sigma-delta]] converter with 2nd order analogue [[Electronic filter|filter]]. | * Audio from an 8 bit [[dither|dithering]] [[Delta-sigma modulation|sigma-delta]] converter with 2nd order analogue [[Electronic filter|filter]]. | ||
* +5V [[Direct Current|DC]] main power. | * +5V [[Direct Current|DC]] main power. | ||
| Line 61: | Line 60: | ||
* [[Original Amiga chipset|OCS]] [[PAL]] video. | * [[Original Amiga chipset|OCS]] [[PAL]] video. | ||
* 512 [[Kibibyte|kB]] [[Static random access memory|SRAM]] RAM for Kickstart used as [[Read-only memory|ROM]]. | * 512 [[Kibibyte|kB]] [[Static random access memory|SRAM]] RAM for Kickstart used as [[Read-only memory|ROM]]. | ||
| − | * 1 | + | * 1 [[Mebibyte|MB]] [[Static random access memory|SRAM]] [[Amiga Chip RAM|ChipRAM]] and 512 [[Kibibyte|kB]] [[Static random access memory|SRAM]] [[Amiga Chip RAM|Ranger/SlowRAM]]. |
== Roadmap == | == Roadmap == | ||
| Line 115: | Line 114: | ||
* [http://en.wikipedia.org/wiki/Minimig Wikipedia:Minimig] | * [http://en.wikipedia.org/wiki/Minimig Wikipedia:Minimig] | ||
| + | * [http://obligement.free.fr/articles/minimig.php Review of the Minimig on Obligement] | ||
* [http://home.hetnet.nl/~weeren001/ Official Website including released code] [http://home.hetnet.nl/~weeren001/downloads.html 'download-link'] | * [http://home.hetnet.nl/~weeren001/ Official Website including released code] [http://home.hetnet.nl/~weeren001/downloads.html 'download-link'] | ||
* [http://www.amiga.org/modules/news/article.php?storyid=7386 Official announcement] | * [http://www.amiga.org/modules/news/article.php?storyid=7386 Official announcement] | ||
Latest revision as of 11:34, 2 October 2010
Minimig 120x120mm PCB board
Minimig (short for "Mini Amiga") is an open source exact FPGA re-implementation of an Amiga 500.
Minimig started life in secrecy around January 2005 as a proof of concept type of deal by the Dutch electrical engineer Dennis van Weeren. He intended Minimig as the answer to the ongoing discussions within the Amiga community on implementing the Amiga Custom Chipset in FPGA and this was released under the open source license GPLv3 on the 25 July 2007.
Contents
Original prototype[edit]
The original Minimig prototype is based on the Xilinx Spartan-3 Starter Kit, the OCS chipset is synthesized in the FPGA. Two pcb boards are attached via the fpga kit expansion ports. The first one holds a 3.3V M68000 type CPU. The second has MMC memory card slot with the use of a small PIC microcontroller as acting disc controller that supports the FAT16 filesystem and does on-the-fly .ADF decoding.
VGA-+-PS2 (joystick etc.)
|
CPU <-> FPGA <-> Microcontroller <-> Flashmemory
|
RAM
The prototype was shown <ref> 060218 amigaroxx.zuurkool.com</ref> at an Amiga meet and loads most Amiga programs although bugs do exist. Coding is done in Verilog because Dennis found VHDL not to be his cup of tea. All done on a PC using Xilinx Webpack software.
Some users have suggested plans to make a joystick style direct-to-tv device for people wanting to play old Amiga games or run software. However a new single board version pcb has been designed, moving away from the Xilinx Starter kit.
Why[edit]
- Run Amiga specific application software to convert files to newer platforms.
- Run software only available on Amiga.
- Games.
- FPGA development experience using Verilog.
- Creating something for the community.
- Proof of Concept.
- Can create new games to take advantages of the new features in Minimig (faster memory, more memory, sprites, colours, etc), while maintaining full compatibility with the classic Amiga.
- Make the Amiga custom chip technology concept available under GPL.
Hardware[edit]
Platform[edit]
- Xilinx Spartan-3 400k gate (XC3S400-4PQ208C) FPGA using 60% capacity.
- Freescale MC68SEC000 (MC68SEC000FU20; MC68SEC000AA20 proposed as replacement part by Freescale), 3,3V, running programable at 7.09379 and 14.18758 MHz. (However there's no 'E' clock, MOVE sr,<EA> is privileged and there is no real replacement instruction. This does not seem to affect any programs as of yet however.)
- Amiga ChipRAM bus and FastRAM merged into a single synchronous bus running at 7.09379 MHz.
- 2 MB 70 ns SRAM organised as 2 524288*16 banks.
- MCU PIC 18LF252-I/SP <ref> 070715 microchip.com</ref> (an alternative would be Atmel AVR) implements a FAT16 disclayout and handles loading of fpga configuration and kickstart. Simulates a floppy to the Amiga by encoding on the fly from .ADF files.
- MMC Flash memory card to load fpga configuration, kickstart and software for the simulated computer.
- 3 LEDs to display the system status - Main power (blue) - Amiga Power (red) - Drive activity (green).
- Video D/A consists of 4 resistors for each color red, green, blue (4 bits/color) and output via VGA connector. Minimig schematics v1 Page3
- Audio from an 8 bit dithering sigma-delta converter with 2nd order analogue filter.
- +5V DC main power.
Ports[edit]
- Spare 4x generic I/O from the fpga
- JTAG for programming chips
- RS232 serial port
- 2x Joystick
- HD15F VGA video
- MMC Flash memory card slot.
- PS/2 connector Keyboard + Mouse
- 3,5 mm audio jack
- +5V DC 2,1 mm cylindrical dc plug power supply inlet.
Implementation[edit]
- OCS PAL video.
- 512 kB SRAM RAM for Kickstart used as ROM.
- 1 MB SRAM ChipRAM and 512 kB SRAM Ranger/SlowRAM.
Roadmap[edit]
| Date | Event |
|---|---|
| 2005-03-06 | Verilog sources coding started. |
| 2005-12-05 | Announcement of the project. |
| 2006 Spring | Verilog sources completed. |
| 2006-06-11 | Screenshoot of schematic for board v1.0 published. |
| 2006-10-15 | Schematic for board v1.0 completed. |
| 2007-06-xx | Sources predicted to be released, but weren't. |
| 2007-07-04 | Last source edit (core). |
| 2007-07-13 | Busy making website for the project. |
| 2007-07-24 | Minimig sources released on the official website. |
Issues[edit]
- Needs a binary copy of kickstart from a real Amiga 500 due that it's copyrighted.
Tools[edit]
Computer to compile the project:
Shuttle barebone, Prescott Pentium 4 3 GHz, 1 GiB Ram, Software Xilinx Webpack version 6.3.03i (2007-07-22 9.1). Time from source .bit configuration file = 2 minutes. Cache and memory speed is vital for fpga software.
See also[edit]
References[edit]
[edit]
External links[edit]
- Wikipedia:Minimig
- Review of the Minimig on Obligement
- Official Website including released code 'download-link'
- Official announcement
- Picture of completed Minimig rev 1.0 board (2006-11-15)
- Site with Minimig related pictures (Dennis + board at Commodore/Amiga shows) (under construction)
- Xilinx ISE Webpack
- AROS Kickstart ROM Replacement bounty (Phase II)
- AROS AmigaOS implementation download
- Announcement of the Minimig project (Amiga.org forum)
- The BoXeR project a Motorola 68040 75 MHz based motherboard.
