Field-programmable gate array - Revision history

Guestblinky: some open-source GAL programming tools; CPLD CPUs; etc.

2025-06-18T23:07:10Z

some open-source GAL programming tools; CPLD CPUs; etc.

Guestblinky: Raspberry Pi Zero form factor

2025-06-07T16:59:53Z

Raspberry Pi Zero form factor

DavidCary: mention related devices

2022-11-23T20:29:07Z

mention related devices

DavidCary: linkfix

2014-09-08T02:26:34Z

linkfix

Gunnar Wolpe: copyedit - style; define term

2012-05-11T20:17:41Z

copyedit - style; define term

DavidCary: merge from Verilog, as suggested

2010-05-18T02:13:25Z

merge from Verilog, as suggested

DavidCary: "open" graphics cards

2009-06-13T22:08:08Z

"open" graphics cards

86.164.235.190: Added link to Lattice

2008-09-17T18:11:46Z

Added link to Lattice

DavidCary: make sections for VHDL and Verilog

2008-06-07T12:12:56Z

make sections for VHDL and Verilog

DavidCary: revert to 04:23, 29 July 2007

2007-12-01T07:20:16Z

revert to 04:23, 29 July 2007

← Older revision		Revision as of 23:07, 18 June 2025
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	* ...		* ...

		+	GALs and CPLDs are still popular for retrocomputing projects
		+	* (a) handling address decoding and other glue logic for "classic" 8-bit processors such as the 6502 and Z80
		+	* (b) replacing the difficult-to-source 74181 and 74182 ALU chips used in many "discrete TTL CPUs", and perhaps further shrinking "discrete TTL CPUs" down to a few chips<ref>
		+	[https://www.bigmessowires.com/cpu-in-a-cpld/ "Tiny CPU in a CPLD"].
		+	</ref><ref>
		+	Jim Mussared. [https://github.com/jimmo/cpld-cpu "cpld-cpu: A simple CPU implemented by discrete CPLD components."].
		+	</ref><ref>
		+	Jim Mussared. [https://blog.jimmo.id.au/2019/01/26/cpld-cpu-part-1.html "CPLD CPU: Part 1, Overview"].
		+	quote: "Unfortunately the ALU chips (74181 and 74182) proved hard to source".
		+	quote: "However the idea is to make it possible to see what’s going on – every signal should have an LED on it."
		+	</ref><ref>
		+	Ed S. [https://hackaday.io/project/25357-opc-1-cpu-for-cpld "OPC-1 CPU for CPLD"].
		+	</ref><ref>
		+	[https://github.com/cpldcpu/MCPU "MCPU - A Minimal 8Bit CPU in a 32 Macrocell CPLD"].
		+	</ref>

		+	Some open-source GAL programming tools (FIXME: very incomplete):
		+
		+	Many people use a Jam STAPL player (running on a laptop or Raspberry Pi) to send the "hex file" over a JTAG port to program a ispGAL or a FPGAs:
		+	* Marcel Groothuis : "Altera Jam STAPL Player with support for 64-bit Windows versions and Raspberry Pi" : https://github.com/margro/jam-stapl
		+	* vladermolaev: "jam2ftdi: Customization of Altera Jam STAPL Byte-Code Player Version 2.5 to work over USB for devices built on FTDI chips." https://github.com/vladermolaev/jam2ftdi
		+	* Muhammet Şükrü Demir: "jam_bc_player: Jam STAPL Byte-Code Player for in-app programming Altera devices in embedded systems... such as STM32 or similar MCUs" https://github.com/dsm/jam_bc_player
		+	* steieio: "Altera JAM STAPL Player" : https://github.com/steieio/altera-jam-player
		+	* "The Jam STAPL Byte-Code Player is coded in the C programming language for 16 bit and 32 bit processors. A specific subset of the player source code also supports some 8 bit processors." https://www.intel.com/content/www/us/en/docs/programmable/683089/current/the-jam-stapl-byte-code-player.html
		+	* [https://web.archive.org/web/20020602040033/http://jamisp.com/ "the Jam STAPL Web Site"] (archived)
		+
		+	* [https://hackaday.com/2008/12/11/how-to-programmable-logic-devices-cpld/ "How-to: Programmable Logic Devices (CPLD)"].
		+	* [https://www.bhabbott.net.nz/atfblast.html "Parallel Port ATF and GAL Programmer"].
		+	* Richard Steven Walz. [http://www.armory.com/~rstevew/Public/Pgmrs/GAL/algo.htm "GAL programming algorithms"].
		+	* [http://www.armory.com/%7Erstevew/Public/Pgmrs/GAL/_ClikMe1st.htm "Manfred Winterhoff's GALBlast"].
		+	* Rune Baeverrud and Woody Johnson. [http://www.pldworld.com/_altera/html/ref/freecore/nosupport/blaster.htm "Build your own ByteBlaster"].
		+	* http://www.pldworld.com/_altera/html/ref/freecore/nosupport/nosupport.html
		+	* [https://elm-chan.org/works/pgal/report_e.html "Simple GAL Programmer"] 1999. Requires parallel port. Also programs PIC16F84.

	== Further reading ==		== Further reading ==

@@ Line 7: / Line 7: @@
 * [[RTL m68k]]
 * [[WikiNode | The Open Graphics Project]] (OGP) is developing graphics cards with fully published specs and open source drivers. Since the first version will be a FPGA, is also collecting information on FPGA programming and interfacing.
 * ...
 * ... ''(Add other open hardware projects I'm forgetting to this list)''

@@ Line 5: / Line 5: @@
 * ...
 * [[Motherboards that run Linux#Balloon_Xscale_ARM.2BFPGA_dev_board | Balloon Xscale + FPGA board]]
 * [[WikiNode | The Open Graphics Project]] (OGP) is developing graphics cards with fully published specs and open source drivers. Since the first version will be a FPGA, is also collecting information on FPGA programming and interfacing.
 * ...
@@ Line 19: / Line 20: @@
 == VHDL ==
 VHDL (VHSIC hardware description language) is commonly used as a design-entry language for designing digital circuits as field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).
 == Further reading ==

@@ Line 4: / Line 4: @@
 * [[Minimig FPGA]]
 * ...
-* [[Projects#Balloon_Xscale_ARM.2BFPGA_dev_board | Balloon Xscale + FPGA board]]
+* [[Motherboards that run Linux#Balloon_Xscale_ARM.2BFPGA_dev_board | Balloon Xscale + FPGA board]]
 * [[WikiNode | The Open Graphics Project]] (OGP) is developing graphics cards with fully published specs and open source drivers. Since the first version will be a FPGA, is also collecting information on FPGA programming and interfacing.
 * ...

@@ Line 1: / Line 1: @@
-FPGA is a logic matrix configurable chip.
+A '''Field-Programmable Gate Array''' (FPGA) is a general purpose logic matrix configurable integrated circuit.  It consists of a collection of logic gates that can be connected together in an almost unlimited number of combinations to produce custom operations that would normally only be possible with full-custom integrated circuits.  Since FPGAs are produced in high volume, they can bring economies of scale to one-off and low volume projects.
 Several open hardware projects use FPGAs, such as
@@ Line 15: / Line 15: @@
 == Verilog ==
 Verilog is a hardware description language (HDL) used to model electronic systems. The language (sometimes called Verilog HDL) supports the design, verification, and implementation of analog, digital, and mixed-signal circuits at various levels of abstraction.
 == VHDL ==
 VHDL (VHSIC hardware description language) is commonly used as a design-entry language for designing digital circuits as field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).
+== Further reading ==
 * [http://en.wikipedia.org/wiki/Field-programmable_gate_array Wikipedia: field-programmable gate array]
 * [http://wiki.opengraphics.org/ The Open Graphics Project wiki]: The Open Graphics Project (OGP) is developing graphics cards with Free-licensed specifications and Free Software drivers. The FPGA development board OGD1, Revision B, uses a Xilinx® Spartan™-III XC3S4000 FPGA (primary FPGA) and a Lattice® LFXP10 non-volatile FPGA (PCI interface)
 * [http://wacco.mveas.com/ "Project VGA"]: Home of the Low Budget, Open Source, VGA Compatible video card. Uses Xilinx Spartan 3 s400 FPGA.

← Older revision		Revision as of 22:08, 13 June 2009
Line 25:		Line 25:

	* [http://en.wikipedia.org/wiki/Field-programmable_gate_array Wikipedia: field-programmable gate array]		* [http://en.wikipedia.org/wiki/Field-programmable_gate_array Wikipedia: field-programmable gate array]
		+	* [http://wiki.opengraphics.org/ The Open Graphics Project wiki]: The Open Graphics Project (OGP) is developing graphics cards with Free-licensed specifications and Free Software drivers. The FPGA development board OGD1, Revision B, uses a Xilinx® Spartan™-III XC3S4000 FPGA (primary FPGA) and a Lattice® LFXP10 non-volatile FPGA (PCI interface)
		+	* [http://wacco.mveas.com/ "Project VGA"]: Home of the Low Budget, Open Source, VGA Compatible video card. Uses Xilinx Spartan 3 s400 FPGA.
		+

	----		----

@@ Line 12: / Line 12: @@
 [[Xilinx]] ...
 [[Altera]] ...
 == Verilog ==

← Older revision		Revision as of 12:12, 7 June 2008
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	[[Xilinx]] ...		[[Xilinx]] ...
	[[Altera]] ...		[[Altera]] ...
		+
		+	== Verilog ==
		+	{{mergefrom\|Verilog}}
		+
		+	== VHDL ==
		+
		+	VHDL (VHSIC hardware description language) is commonly used as a design-entry language for designing digital circuits as field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).

← Older revision		Revision as of 07:20, 1 December 2007
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−	~~trnooloca~~
	FPGA is a logic matrix configurable chip.		FPGA is a logic matrix configurable chip.