Editing JTAG
Jump to navigation
Jump to search
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
Latest revision | Your text | ||
Line 1: | Line 1: | ||
− | The Joint Test Action Group (JTAG) standardized a 5 | + | The Joint Test Action Group (JTAG) standardized a 5 pin boundary-scan test port as IEEE Std. 1149.1, "Standard Test Access Port and Boundary-Scan Architecture". |
While originally intended for boundary-scan testing of PCB assemblies, to replace bed-of-nails testing, the JTAG port included in many popular microprocessors is also often used for programming and debugging. | While originally intended for boundary-scan testing of PCB assemblies, to replace bed-of-nails testing, the JTAG port included in many popular microprocessors is also often used for programming and debugging. | ||
Line 5: | Line 5: | ||
[http://hogyros.de/?q=node/167 "If you have information on how to connect a JTAG probe to a Nokia phone, please let me know."] | [http://hogyros.de/?q=node/167 "If you have information on how to connect a JTAG probe to a Nokia phone, please let me know."] | ||
− | There are five | + | There are five pins: |
* TCK/clock | * TCK/clock | ||
* TMS/mode select | * TMS/mode select | ||
Line 18: | Line 18: | ||
== 20 Pin JTAG PinOut == | == 20 Pin JTAG PinOut == | ||
+ | |||
+ | Which one of these is right? | ||
+ | |||
+ | Pin Function Pin Function | ||
+ | 1 TRST 2 GND | ||
+ | 3 TDO 4 GND | ||
+ | 5 TDI 6 GND | ||
+ | 7 TMS 8 GND | ||
+ | 9 TCK 10 GND | ||
+ | 11 VPP_E 12 GND | ||
+ | 13 A/W 14 GND | ||
+ | 15 User 0 16 GND | ||
+ | 17 Rdy/Bsy 18 GND | ||
+ | 19 User 1 20 Vcc | ||
1 +3.3 V 2 +3.3 V | 1 +3.3 V 2 +3.3 V | ||
Line 28: | Line 42: | ||
15 nRST 16 GND | 15 nRST 16 GND | ||
17 -- 18 GND | 17 -- 18 GND | ||
− | 19 -- 20 GND | + | 19 -- 20 GND |
+ | |||
== external links == | == external links == | ||
Line 35: | Line 50: | ||
* [http://www.arm.com/support/faqdev/1336.html "When designing development boards what style JTAG connector should I use?"] The 20-pin JTAG connector. | * [http://www.arm.com/support/faqdev/1336.html "When designing development boards what style JTAG connector should I use?"] The 20-pin JTAG connector. | ||
* [http://www.embedded.com/story/OEG20021028S0049 "Introduction to JTAG"] by Rob Oshana 2002 | * [http://www.embedded.com/story/OEG20021028S0049 "Introduction to JTAG"] by Rob Oshana 2002 | ||
− | * [http://hri.sourceforge.net/tools/jtag_faq_org.html "JTAG FAQ"] by Stas Khirman 2004 | + | * [http://hri.sourceforge.net/tools/jtag_faq_org.html "JTAG FAQ"] by Stas Khirman 2004 |
* [http://k9spud.com/jtag/ a parallel port JTAG Debugger circuit for Philips LPC2xxx ARM microcontrollers.] by K9JTAG (uses Schmitt trigger inverters, so it can connect 3.0 V target boards to a standard 5.0 V parallel port) | * [http://k9spud.com/jtag/ a parallel port JTAG Debugger circuit for Philips LPC2xxx ARM microcontrollers.] by K9JTAG (uses Schmitt trigger inverters, so it can connect 3.0 V target boards to a standard 5.0 V parallel port) | ||
* [http://diygadget.com/store/building-simple-jtag-cable/info_12.html parallel port JTAG "Building Simple JTAG Cable"] (resistors only) | * [http://diygadget.com/store/building-simple-jtag-cable/info_12.html parallel port JTAG "Building Simple JTAG Cable"] (resistors only) | ||
Line 44: | Line 59: | ||
* [http://freelabs.com/~whitis/electronics/jtag/ the JTAG protocol] by Mark Whitis | * [http://freelabs.com/~whitis/electronics/jtag/ the JTAG protocol] by Mark Whitis | ||
* [http://scienceprog.com/avrjtag-clone-in-action/ "Building AVR Jtag clone"] includes schematics and firmware. | * [http://scienceprog.com/avrjtag-clone-in-action/ "Building AVR Jtag clone"] includes schematics and firmware. | ||
− | + | ||
− | |||
− | |||
− | |||
---- | ---- |