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[http://essayfast.com/ custom essay writing]</div>Adams Quinnhttp://www.opencircuits.com/index.php?title=Relay_CPU&diff=22183Relay CPU2011-12-27T22:50:22Z<p>Adams Quinn: </p>
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<div>[[File:Main-G5Q-14.jpg|right]]<br />
A '''relay CPU''' is a CPU built mostly or entirely out of [[relays]].<br />
<br />
While at one time relays were the best available component for building a computer,<br />
nowadays one of the few advantages of a relay CPU over other CPU implementations is that you can see it working (very educational) --<br />
building a CPU on a FPGA or other integrated chip makes it use less power, run faster, cost less, etc. than a relay CPU.<br />
<br />
Harry Porter built his<br />
[http://web.cecs.pdx.edu/~harry/Relay/ "Relay Computer"]<br />
out of 415 Relays, all identical 4PDT.<br />
<br />
Jon Stanley built <br />
[http://www.electronixandmore.com/project/relaycomputertwo/index.html "Relay Computer Two"],<br />
a relay computer built from 281 relays.<br />
<br />
Is it possible to build a relay CPU from significantly fewer relays?<br />
In particular, is it possible to build a relay CPU<br />
from 256 relays or less?<br />
From 100 relays or less?<br />
<br />
Perhaps we should have 2 categories:<br />
* What's the minimum number of relays in a relay-only CPU?<br />
* What's the minimum number of relays in a diode-relay CPU?<br />
<br />
== lots of miscellaneous tibits that seem kind of related to building a relay CPU ==<br />
<br />
What is a good simulator for a relay computer?<br />
<br />
Tofu relay circuit simulator.<br />
[http://meatfighter.com/tofu/]<br />
[http://meatfighter.com/tofu/tutorial/index.html]<br />
<br />
http://en.wikipedia.org/wiki/Quite_Universal_Circuit_Simulator<br />
<br />
tkgate open-source gate-level schematic entry and simulator<br />
[http://www.tkgate.org/]<br />
<br />
http://electronics.stackexchange.com/questions/7022/circuit-simulation-software<br />
<br />
<br />
Bouncing is not a problem inside a relay CPU,<br />
but it can be a problem when you try to interface a relay CPU to a semiconductor RAM.<br />
What is a good method for<br />
[http://www.ganssle.com/debouncing.pdf debouncing]?<br />
<br />
<br />
<br />
[http://www.kk.org/thetechnium/archives/2009/02/amish_hackers_a.php "Amish Hackers"]<br />
claims that <br />
<q>The Amish call this pneumatic system "Amish electricity."</q><br />
<br />
One of the commenters said "... there are pneumatic equivalents to electrical devices. Air - is there anything it can’t do?"<br />
<br />
I wonder how difficult it would be to build a CPU that, instead of being built of ICs or discrete transistors or relays, was built from pneumatically-powered devices.<br />
<br />
Then, of course, put it in a case that looks like this:<br />
"Steampunk Frankenstein computer casemod"<br />
http://blog.makezine.com/archive/2009/02/frankenstein_casemod.html<br />
<br />
<br />
[http://www.fastchip.net/howcomputerswork/p1.html "How Computers Work"]<br />
by Roger Young<br />
uses a relay computer in many examples.<br />
<br />
<br />
Some nice features that will make it easier to find and fix the inevitable mistakes people make when wiring up something as complicated as a CPU:<br />
* single-step-ability<br />
* breakpoints<br />
* lots of LEDs (If you make the traditional hard-wired diode array for microcode, building it out of LEDs might be cool)<br />
* minimum # of chips to wire together<br />
<br />
* testability: single-step, breakpoints on program address, breakpoints on data address, breakpoints on data write address ... what other testability things are useful?<br />
<br />
<br />
You need to balance:<br />
* Many programmers appreciate lots of general-purpose registers, rather than needing to remember a bunch of quirks associated with each register. Since memory is slow, keeping the "working set" of data in registers helps reduce the pressure on the memory interface (von Neumann bottleneck).<br />
* Fewer registers<br />
--> directly easier to build because you don't have to build and test those registers.<br />
--> indirectly easier to build because there is less stuff (microcode, etc) needing to select *which* register.<br />
* instructions that only work with *some* registers (quirky) --> less stuff needed to select *which* register.<br />
<br />
On the other hand, if you implement the registers in a small SRAM,<br />
having more than a minimum number is also helpful:<br />
* no need for complicated indirect indexed addressing modes<br />
--> indirectly easier to build because fewer addressing modes to build and test.<br />
<br />
Also,<br />
* more registers makes the "carry bit" or other status bits less necessary.<br />
<br />
<br />
<br />
building a computer (except for the RAM and program storage) out of relays:<br />
we have 2 slightly-contradictory desires:<br />
<br />
(a) It would be nice to use the fewest number of relays, because each relay will need<br />
to be hand-wired, and each "on" coil dissipates power.<br />
<br />
(b) It would be nice to do a bunch of work on each clock cycle, so we can get the<br />
same amount of work done in fewer clock cycles, reducing wear-and-tear on<br />
the relays ... and if the relays are optimally driven (approximate with "snubber" in series with coil, where the snubber is a parallel RC), it takes less power<br />
to "hold" the relay than to switch states.<br />
<br />
I suspect that balancing these 2 requirements is very similar to optimizing<br />
similar requirements for minimizing power in purely solid-state logic.<br />
<br />
<br />
<br />
<br />
<br />
relay computer<br />
<br />
2008-05-22:<br />
DAV:<br />
thinking about building a cpu out of relays.<br />
standard 4 phase clock should work.<br />
But can relays support the setup and hold time requirements for 2 phase clock?<br />
<br />
Say we have a series of transparent latches.<br />
(They will have some combinational logic between them -- I'll ignore the combinational logic while trying to answer this question).<br />
<br />
Each "layer" of transparent latches is transparent on the "opposite" phase.<br />
<br />
On the falling edge of the clock:<br />
low-transparent latches become transparent, letting their inputs flow through to their outputs. (They may switch states).<br />
hi-transparent latches go into "hold" state, maintaining that bit until the rising edge of the clock. (They don't switch states).<br />
<br />
So ... for 2 phase clock to work,<br />
the low-transparent latches need to hold their "hold" bit long enough for the hi-transparent latches to grab it.<br />
<br />
<br />
one teensy glitch:<br />
during transitions, with a break-before-make relay,<br />
there is a short time when the output is "disconnected" -- typically representing "0".<br />
Is that going to cause a problem?<br />
No.<br />
+------------+<br />
| |<br />
0 --|0\ |<br />
> >--+ |<br />
1 --|1/ | |<br />
+--|0\ |<br />
> >--+------- Q<br />
D ----------|1/<br />
|<br />
CLK ---------+<br />
<br />
This is a CLK-Hi-transparent latch.<br />
<br />
CLK _____/---------\_________<br />
<br />
D ________XXXXXXXX-----------<br />
<br />
Q _____________________/-----<br />
<br />
I suspect relays will have a pretty high latency -- after the CLK (driving the coil) changes state, it will be a while before the contact is broken.<br />
<br />
<br />
So:<br />
transparent-to-hold transition:<br />
<br />
C relay coil changes state.<br />
Sometime later, the D contact breaks contact, and Q become the "not connected" state.<br />
Sometime after that, the Q contact makes contact, and Q becomes the held state.<br />
Hopefully the time between the break and the make is short enough that the short glitch at the Q relay coil isn't enough for it to change state.<br />
<br />
After the D contact breaks contact, clearly the D contact is in the "don't care" state.<br />
<br />
hold-to-transparent transition:<br />
C relay coil changes state.<br />
Sometime later, the Q contact breaks contact, and Q becomes the "not connected" state.<br />
Sometime after that, the D contact makes contact, and Q becomes the transparent state.<br />
Hopefully the time between the break and make is short enough that the short glitch at the Q output isn't enough to affect stuff downstream.<br />
<br />
master-slave bit:<br />
first latch transparent-to-hold, 2nd latch hold-to-transparent transition:<br />
... doesn't seem to be a problem.<br />
<br />
first latch hold-to-transparent, 2nd latch transparent-to-hold:<br />
Both C relay coils change state.<br />
Sometime later, there is a break in the contact, and the internal Q and the outer Q both become the "not connected" state.<br />
Sometime after that, the 2nd latch Q contact makes contact, and Q becomes the held state.<br />
Hopefully the time between the break and the make is short enough that the short glitch at the 2nd Q relay coil isn't enough for it to change state.<br />
<br />
----<br />
<br />
2010-09-22:DAV:<br />
Would the ideal computer for<br />
implementing Wheeler's diverse double compiling ("DDC")<br />
( wheeler-trusting-trust-ddc.pdf )<br />
be a relay computer?<br />
Especially for Wheeler's comment that<br />
"Future potential work includes recompiling an entire operating system as the compiler-under-test".<br />
There are 2 operations that need to be trustworthy:<br />
* compiling some ancestor source code to a compiler executable<br />
* comparisons.<br />
<br />
Perhaps it would be better to build 2 separate relay machines,<br />
each one dedicated to a different part:<br />
* a "compare" relay machine:<br />
Compares every byte on 2 MMC/SD cards and confirms that they are identical.<br />
Perhaps gives some sort of display to indicate which byte is different.<br />
* a "compile" relay machine:<br />
runs a compiler executable (from one SD/MMC card?),<br />
with the source code to some ancestor compiler (on another SD/MMC card?),<br />
and store the resulting executable (to a third SD/MMC card?).<br />
<br />
Then the DDC process is something like:<br />
* somehow (?) create a trustworthy compiler executable, in relay computer machine code, on one MMC/SD card<br />
* somehow (?) store a compiler source code on another MMC/SD card<br />
* plug both cards and an output blank card into the relay computer, and<br />
generate the ancestor compiler<br />
plus the boot code and everything else required to start a working environment<br />
(targeted to the fast computer).<br />
* plug the ancestor SD/MMC card into a fast computer, and boot off that card.<br />
Use that trustworthy environment<br />
to more rapidly executed the later stages of the DDC process, and<br />
to inspect source code.<br />
<br />
So does this necessarily mean the relay computer needs to be able to run a C compiler?<br />
(perhaps TCC or the bootstrap for GCC)?<br />
Or is it possible for it to run, say, a Forth compiler?<br />
(I suspect that would require less RAM on the relay machine).<br />
That seems to require that a bootstrap C compiler be written<br />
with its source code in Forth.<br />
(Either that Forth source is compiled on the relay machine,<br />
or that Forth source is compiled on the fast computer).<br />
<br />
----<br />
<br />
2011-03-10:DAV:<br />
I come across yet another relay computer:<br />
http://nablaman.com/relay/<br />
<br />
3 x 8-bit accumulator registers,<br />
2 x 12-bit registers (for index, addresses and jumps)<br />
plus a 12 bit program counter and 12 bit stack register.<br />
<br />
DAV: I think it would be interesting to<br />
re-arrange the 3 x 8-bit register bits to make 2 x 12-bit registers,<br />
so "everything" is 12 bits.<br />
<br />
Another non-multiple-of-8 machine I came across today:<br />
The Six Bit Machine<br />
by Jack Eisenmann<br />
http://web.me.com/teisenmann/sixbit/main.html<br />
<br />
----<br />
<br />
2008-12-15:DAV:<br />
Yet another idea for a relay computer:<br />
wacky mix of relays and 74x ICs.<br />
* use 74x shift registers to hold bits (registers, PC, IR, interrupt request, perhaps carry bit)<br />
* use relays to guide the bits in the correct direction -- in particular, the output of one shift register to the input of the "deeper" register when doing a "push"; the output of one register to the input of a shallower register when doing a "pop".<br />
* Use a random mix of relays and 74x 4:1 muxes to implement more complex logic.<br />
During operation,<br />
* one big *chunk* as IR is latched and relay configuration is set up.<br />
* then 8 (or perhaps 12 or 16 or 24 or 48) quiet (or quieter) pulses as bits are shuffled out of some registers and into other registers.<br />
<br />
Hopefully building it as a "serial computer" will make it smaller.<br />
<br />
<br />
<br />
----<br />
<br />
2008-08-22:DAV:<br />
Applications for a relay computer:<br />
* cryptographic applications -- because I can *see* it work, it's far more difficult for malware or keyloggers.<br />
** AES encryption and decryption<br />
** public/private key generation<br />
** public/private key encryption and decryption<br />
<br />
What sorts of operations do we need to support to be able to do AES reasonably efficiently?<br />
<br />
-----<br />
<br />
2009-02-03:DAV:<br />
<br />
Inspired by <br />
Magic-1 http://www.homebrewcpu.com/<br />
<br />
I make my own goals for my relay computer:<br />
<br />
Goals:<br />
<br />
* Touch the magic. Gain a deeper understanding of how computers work.<br />
<br />
* Compactness. Physically small and simple.<br />
Unlike Bill, I'm not so interested in the "density" of each opcode<br />
individually (Huffman-like compression).<br />
I'm even more interested in the "density" of the instruction<br />
set as a whole (LZ77-like compression), so I insist on extremely low overhead<br />
for subroutines.<br />
<br />
* TTL and transistors and relays rather than FPGA.<br />
FPGAs do sound fun, but I want a system where I can touch and see and hear<br />
everything it is doing, rather than a mysterious black box -- I want<br />
(literally) every bit<br />
visible.<br />
Perhaps FPGA for the next one.<br />
<br />
* simplicity.<br />
<br />
* Build something real.<br />
<br />
Like Bill, "At the end of the day, I wanted a working, and useful, machine<br />
that I understood completely. Oh, and it had to have a real front panel with<br />
lots and lots of cool blinky lights."<br />
-- Bill Buzbee<br />
<br />
<br />
<br />
[relay computer]<br />
<br />
2008-10-19:<br />
found even cheaper relays at All Electronics:<br />
<br />
$0.50 24 VDC SPDT PC MOUNT POWER RELAY; 480 Ohm coil; completely uncovered so I can see what's going on.<br />
http://www.allelectronics.com/make-a-store/item/RLY-275/24-VDC-SPDT-PC-MOUNT-POWER-RELAY/-/1.html<br />
<br />
2009-11-30:<br />
$1.00 5VDC DPDT SUB-MINI RELAY; 14.9 x 7.4 x 9.7mm high. PC pins.; 178 Ohm coil; CAT# RLY-538 (All Electronics 2009)<br />
$1.00 24VDC DPDT DIP RELAY; 0.63" x 0.38" x 0.31" high. ( 16 x 9.7 x 7.9 mm ); 2850 Ohm; CAT# RLY-505 (All Electronics 2009)<br />
<br />
<br />
Jon Stanley suggests saving money by getting relays using eBay.<br />
<br />
I am surprised that reed relays cost more than PCB relays,<br />
since it seems that reed relays have fewer parts and so would cost less.<br />
<br />
<br />
2008-08-10:DAV:<br />
what about "latching relays" ?<br />
Wouldn't that implement a register array in fewer relays than non-latching relays?<br />
Does it make sense to build Mueller C-elements for asynchronous computing out of latching relays?<br />
<br />
<br />
<br />
wire spring relay<br />
http://en.wikipedia.org/wiki/Wire_spring_relay<br />
claims that<br />
"Reed relays are better suited to data storage."<br />
<br />
reed relay<br />
http://en.wikipedia.org/wiki/Reed_relay<br />
claims that<br />
"reed relays can switch much faster than relays with armatures"<br />
<br />
<br />
----<br />
<br />
2008-09-06:DAV:<br />
I discover<br />
"Relay Computer Two"<br />
by Jon Stanley<br />
http://www.electronixandmore.com/project/relaycomputertwo/index.html<br />
a relay computer built from 281 relays<br />
...<br />
That is far fewer relays than I thought were needed.<br />
<br />
Registers:<br />
All registers are "transparent".<br />
("master/slave" would require twice as many registers).<br />
<br />
<br />
DAV: (Would it make any sense to re-arrange the muxes so that<br />
PC1 is hard-wired to the incrementer,<br />
the incrementer is hard-wired to the address bus,<br />
and the address bus is muxed between PC2 or MAR?<br />
Chuck Moore seems to like that arrangement ...<br />
because it is obviously simpler.)<br />
<br />
<br />
.<br />
. +-<---[increment]-------<-+<br />
. | |<br />
. +->->[PCR1]->[PCR2]->|\ |<br />
. | >->+----> RAM address<br />
. ...->[MAR ]->|/<br />
. |<br />
. LSB<br />
<br />
<br />
Things it lacks that I wish it had:<br />
* it's difficult to lookup A = B[C], because there are are no indexed loads.<br />
* it's difficult to lookup A[B] = C, because there are no indexed stores.<br />
Those 2 things can be done if we "cheat" and write self-modifying code ... which this architecture makes fairly easy to do.<br />
<br />
* Subroutine calls look unncessarily difficult.<br />
<br />
<br />
* One solution to the "backdriving" problem:<br />
use lots of diodes -- perhaps LEDs. If every input to a block of logic goes through a diode, then it's impossible for that block to "backdrive" current through that diode.<br />
Since relays pull ~40 mA, pick LEDs that can handle 40 mA ... or pair up cheaper 20 mA LEDs.<br />
Since some (typical?) LEDs can block max 5V reverse,<br />
(a) use 5V relays and also (b) make sure we put flyback diodes (the same kind of LED is fine) on every coil.<br />
<br />
Say we go even futher and try to build "diode-relay logic" -- would that save a significant number of relays?<br />
DAV: diode-relay logic could be something like this:<br />
every block of logic has a SPDT or 4PDT relay near the output.<br />
The "common" of the switch connected to +24V.<br />
The other 2 lines (the NO and the NC terminals) of the switch are the 2 outputs, the signal and its negation.<br />
Many functions can be built using just that one SPDT relay and a bunch of input diodes ORed together to the coil, where each diode is connected to some signal, or to the negation of that signal -- that gives us OR and NOR outputs, and arbitrary inverts on each input -- so it can implement AND and NAND also. 2 layers of such logic give any possible Boolean function on the inputs.<br />
For example, 3-in XOR requires 5 SPDT relays.<br />
Is there a better way to build "diode-relay logic"?<br />
<br />
Probably, since all possible 3-input logic gates (including 3-in XOR) can be built using only 3 relays and no diodes:<br />
Each input connects to its respective coil (the other end of the coils connect to ground), so there is no backdriving problem.<br />
The first relay is 4PDT.<br />
Its 8 inputs (NC and NO terminals) arbitrarily connected to either nothing or +24V in order to select which particular 3-input logic gate we are implementing today.<br />
The second relay is 2PDT.<br />
The 2 common outputs of the 2PDT relay feed into the 2 inputs (NC and NO) of the third (final) SPDT relay.<br />
The common output of the final SPDT relay is the output signal.<br />
(Alas, it only generates the signal, and not also its complement).<br />
(yeah, a lot of words; a schematic would be better).<br />
<br />
<br />
Consider:<br />
eliminating the 16 bit MAR register,<br />
and adding 8 bits to the A, B, and C registers<br />
(for a net addition of 8 bits).<br />
Then you have a "pure" 16 bit machine (more or less).<br />
Make "load" always use the C as the address register, while "store" always uses A as the address register.<br />
Because *before* we do a calculation, C is usually free (it will be overwritten by the result of the calculation) -- but *after* we do the calculation, C holds the result we usually want to store, and so we can save 1 instruction in the program by using something other than C for the temporary address register.<br />
<br />
I'm hoping that losing MAB will be compensated for by making indexed addressing easier -- in particular, pointer dereferencing and array dereferencing and simple memory copies.<br />
(Such addressing uses load and store, but suppresses the load of C and instead uses the address already in C).<br />
<br />
<br />
-----<br />
<br />
[consider building]<br />
DAV:<br />
as warm-up for building a relay computer,<br />
consider building a relay clock.<br />
<br />
Perhaps<br />
use the 60 Hz line frequency as input.<br />
Does toggling the relay at 60 Hz wear it out too quickly?<br />
... Perhaps, an LCR + relay oscillator running at 1 or 2 Hz would last much longer ... perhaps with a bit of input from the 60 Hz line frequency to phase-lock it.<br />
<br />
...<br />
If we have a ring oscillator of relays, with (say) 12 relays tuned to give (say) 5 Hz for the rest of the clock --<br />
with a small amount of 60 Hz line frequency to phase-lock --<br />
does that merely postpone wearout by a factor of 12?<br />
<br />
----<br />
<br />
[relay computers]<br />
http://www.juliantrubin.com/bigten/zusecomputer.html<br />
<br />
<br />
<br />
DAV: Does it make sense to write software to semi-automatically "optimize" a relay computer design?<br />
... peephole optimizations: 2 relays driven by one signal can sometimes be combined into one relay ... Generating A and /A can be done in several ways ... wired-or can *sometimes* be done -- a computer program can automatically test and see if those conditions are met ... 4 independent copies of A can be generated in a 4PST relay -- this may require fewer relays than a single copy of A that is carefully buffered in many places ...<br />
<br />
global optimizations: given a single global clock signal, what is the maximum number of states that a set of n relays can step through before repeating a state? Can that be used to generate a state counter or program counter that uses fewer relays than the "classic" designs?<br />
(This is similar to the "busy beaver" problem).<br />
<br />
----<br />
<br />
[relay computer]<br />
2008-12-21:DAV:<br />
<br />
What if we<br />
(a) store all bits in ICs (say, a MMC card, a Ramtron FRAM, and a bunch of shift registers), but<br />
(b) did everything else (ALU ops, IR latch control signal decoding, etc.) with relays?<br />
<br />
Well, clearly we must have some sort of IC-to-relay and some sort of relay-to-IC interface.<br />
<br />
Relay-to-IC is pretty simple: either use 5 V supplies for both, or else use a resistor divider / diode clipping to convert 12 V or 24 V relay output to 5V or 3.3 V IC input.<br />
The tricky bit is relay bounce, and that is irrelevant for everything except the clock input. Perhaps somehow use 2 wire clock (which is immune to relay bounce) and somehow convert to a clean 1 wire clock for the ICs.<br />
<br />
IC-to-relay is a bit trickier.<br />
Traditional approach is to use a transistor per IC output.<br />
<br />
What about, in particular, the<br />
$2.41 TPIC6595 8-Bit Shift Register?<br />
<br />
It has one special output:<br />
SER OUT seems to be rated at only 0.020 A (but both source and drain), and restricted to slightly beyond 0 to 5.0 V.<br />
So a minimum resistance of R=V/I = 5 V / 0.020 A = 250 Ohms.<br />
<br />
Eight Power DMOS Transistor Outputs of<br />
0.25 A Continuous Current -- at 24 V, that implies an output load of a minimum of R=V/I = 24 V / 0.25 A = 96 Ohms (minimum) -- so plenty powerful enough to drive a 480 Ohm 24 V coil. (I think the inductance of the coil is irrelevant to this IC, as long as the coil has a proper flyback diode).<br />
1.5 A Pulsed Current Per Output (for up to 1 ms at 10% duty cycle)<br />
(open drain -- this constrains me to using "open" and "GND" to represent 1 and 0 or 0 and 1.<br />
);<br />
when "open", it tolerates drain-source voltage up to 45 V (so apparently it could directly drive 24 V relays ... if the other side of the coil is connected to +24 V).<br />
<br />
One special power input:<br />
Logic supply voltage: must be about 5.0 V.<br />
<br />
5 signal inputs:<br />
0.85 Vcc or above for 1,<br />
0.15 Vcc or below for 0.<br />
<br />
----<br />
<br />
forth on relay computer?<br />
<br />
----<br />
<br />
Put 1 LED at each coil for easier visibility?<br />
<br />
<br />
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<br />
<br />
<br />
DAV:<br />
I keep thinking in terms of "registers" ...<br />
but to minimize the number of relays, I think I'm going to have to minimize the number of registers.<br />
And yet ... I want some sort of indexed load and indexed store,<br />
which makes programming much simpler (stacks, arrays, etc.).<br />
So I think we have only 3 choices:<br />
* keep the index (and the PC) in special registers<br />
* keep the index (and the PC) in the same main memory (serial FRAM?) as everything else<br />
* keep the index in some other memory other than the main memory.<br />
<br />
If we keep our "no registers in the relays, all data stored in the serial FRAM (perhaps in the FRAM address register)" concept,<br />
then perhaps our minimum cycle time is:<br />
<br />
indexed store:<br />
* clock "load" opcode out of program memory into instruction register IR<br />
* clock immediate address of the index out of program memory into address register<br />
* clock address from the address register into data memory<br />
* clock data into data memory<br />
<br />
indexed load:<br />
* clock "load" opcode out of program memory<br />
* clock immediate address of the index out of program memory into address register<br />
* clock address from the address register into data memory<br />
* clock data from data memory<br />
<br />
[relay computer]<br />
"How to pick a relay"<br />
http://www.leachintl2.com/english/english2/vol6/properties/how4.htm<br />
"There is no relay contact that can be used for switching all load levels.<br />
Each load level requires tailoring of the contacts for that specific application.<br />
Contacts rated as capable of handling "dry circuit to 2A" loads will do so.<br />
They cannot, however, handle loads that go from 2A to dry circuit levels.<br />
Knowing this might have prevented one misapplication that luckily had only embarrassing consequences."<br />
<br />
[relay computer]<br />
Relay General Application Guidelines<br />
http://www.tai-shing.com.tw/technical/relay.htm<br />
<br />
<br />
<br />
[build a relay computer]<br />
While using SPNO relays (single-pole, single-throw, normally open relays)<br />
may be the smallest and cheapest way to store<br />
register bits ...<br />
SPNO relays are not "universal".<br />
Perhaps it would be interesting to use<br />
DPDT or 4PDT registers to store register bits.<br />
(a) Using a single kind of relay for everything requires using a universal relay.<br />
(b) Using a relay with more than 1 pole gives me a *separate* input and output for a register,<br />
so I can directly hook the output to a data bus<br />
without worrying about "backfeeding" signals flipping bits in the register.<br />
<br />
== Further reading ==<br />
<br />
"In this world there are few people working on making computers simple to understand, simple to build, and simple to program."<br />
-- Jeff Fox http://www.ultratechnology.com/forth.htm<br />
<br />
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[http://e-writer.org/ essay writers]</div>Adams Quinnhttp://www.opencircuits.com/index.php?title=CUI&diff=22182CUI2011-12-27T22:50:09Z<p>Adams Quinn: </p>
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