From Open Circuits
The Joint Test Action Group (JTAG) standardized a 5 signal boundary-scan test port as IEEE Std. 1149.1, "Standard Test Access Port and Boundary-Scan Architecture".
While originally intended for boundary-scan testing of PCB assemblies, to replace bed-of-nails testing, the JTAG port included in many popular microprocessors is also often used for programming and debugging.
There are five signals:
- TMS/mode select
- TDI/data in
- TDO/data out
- TRST/reset (optional), when driven low, resets the internal state machine.
Except for TCK, all other JTAG lines should be pulled high via a resistor.
WARNING: unconfirmed pinout. Please add links to pinout standard.
 20 Pin JTAG PinOut
1 +3.3 V 2 +3.3 V 3 nTRST 4 GND 5 TDI 6 GND 7 TMS 8 GND 9 TCK 10 GND 11 -- 12 GND 13 TDO 14 GND 15 nRST 16 GND 17 -- 18 GND 19 -- 20 GND
 external links
- the OpenJTAG wiki ( http://openjtag.net/ )
- "When designing development boards what style JTAG connector should I use?" The 20-pin JTAG connector.
- "Introduction to JTAG" by Rob Oshana 2002
- "JTAG FAQ" by Stas Khirman 2004 includes a section on 14 pin, 20 pin, and 8 pin JTAG headers
- a parallel port JTAG Debugger circuit for Philips LPC2xxx ARM microcontrollers. by K9JTAG (uses Schmitt trigger inverters, so it can connect 3.0 V target boards to a standard 5.0 V parallel port)
- parallel port JTAG "Building Simple JTAG Cable" (resistors only)
- "JTAG Bus Description"
- OpenWRT wiki: JTAG Cables
- the Jtag-Arm9 project at Sourceforge gives instructions and photographs of a Home made JTAG interface (also shows an example of prototyping using SMT IC)
- the JTAG protocol by Mark Whitis
- "Building AVR Jtag clone" includes schematics and firmware.
- Embecosm publishes a "SystemC JTAG interface specification" to simplify debugging complex chips.
- lists a variety of JTAG Pinouts
- Debugging with JTAG (CELF presentation)
- Open JTAG Project Make your proper high speed JTAG